Semiconductor memory devices have undergone various design changes in terms of package density, operating speed, or power/current dissipation. Different types of non-volatile memory devices have been developed to store information. Non-volatile memory retains stored data even after the power is removed from the device. A memory device should have an increased storage density with reduced read and write durations.
Flash memory cells can be classified into NAND type, NOR type, AG-AND (Assist Gate-AND) type. The NAND flash memory cells are useful in large scale integration. The NOR flash memory cells include cell transistors that are connected in parallel between bit lines and ground lines. The NOR flash memory cells provide high-speed of operations. The AND type flash memory is advantageous for its high speed writing (10 megabytes per second) and large volume storage capacity (4 GB), smaller chip size (memory cell area of 0.016 micro sq. meter).
As NAND flash memory cells can be easily integrated and made at a low cost, it is advantageous to apply NAND-type flash memories to a large scale supplementary memory device. These days various NAND-type flash memories are provided with various functional options to comply with the various requirements.
U.S. Pat. No. 6,097,666 discloses a method to provide a memory capability of reducing erase time, write time and test time without raising the chip cost and making the address inputting operation complicated. Another object of this present disclosure is to provide a semiconductor memory device capable of freely setting the size of a selected block and selectively affecting the erase, write and test operations with respect to a plurality of blocks. Therefore, this method provides a technique for selecting multiple blocks for different operations. However, it does not provide options for selection of commands to enhance the performance of memory. Moreover, the patent is on memory device and not on the controller.
U.S. Pat. No. 6,400,624 discloses a method for testing a multi-level memory. This includes storing multi-level data in a plurality of memory cells of the multi-level memory and reading from configure registers initial values of a plurality of performance variables. The performance variables set operating parameters of the multi-level memory. This method is therefore a technique for comparing the reference stored in the configuration registers for finding the performance.
U.S. Pat. No. 6,446,177 discloses a memory system using semiconductor memory to be used for the purpose of protecting copyrights. This also relates to a control method of electrically erasable and programmable nonvolatile semiconductor memory, especially useful for use to NAND EEPROM (Electrically Erasable and Programmable Read-Only Memory). Thus, this reference discloses a method of copyright protection by identification.
U.S. Pat. No. 6,629,224 relates to a method for operating a semiconductor memory device having a plurality of operating modes. Commands are accepted twice by a semiconductor memory device. The number of operating modes is narrowed down by the first command. At this time, a part of the circuit necessary for performing a predetermined operating mode among the narrowed operating modes is operated. Then, an operating mode is determined by the second command. When the operating mode is a predetermined operating mode, the remainder of the circuit is operated. This method reduces the terminals for inputting the commands and addresses.
U.S. Pat. No. 6,591,330 relates to a system and method for handling data storage on a plurality of different types of flash devices. More particularly, to a system and method which manage the storage and retrieval of information on flash devices having different sizes of erasable units and/or read/write units, enabling them to behave as flash disks. Therefore, this method discloses the controller system capable of the flash/memory controller with selectable different size of the read/write units. However, this method does not address the usage of different options available inside the NAND itself for same function of read/write/copy.
U.S. Pat. No. 6,424,569 discloses a technique for selectable option, added to a memory cell, such as a multilevel NAND flash cell, that allows the user to select whether to optimize the programming time or the data integrity. A mode selection mechanism can switch the programming mode of each cell. A first programming mode programs the cell with a first programming voltage and maintains at least fifty percent of the maximum data margin. A second programming mode programs the cell with a second programming voltage and maintains at least eighty five percent of the maximum data margin. Thus, this method provides a selectable programming time, however does not provide for user selectable commands of memory.
U.S. Pat. No. 6,507,514 relates to an integrated circuit chip suitable for use in either a single chip packaged configuration or a multi-chip packaged configuration. The chip has a conventional memory circuit portion and a control circuit portion.
U.S. Pat. No. 6,724,682 discloses a NAND type flash memory device that can properly operate in response to a user's requirements to page sizes and block sizes, and have various multiple speeds of operation mode according to options. The structure and operation method of a NAND type flash memory device having two or more page sizes and block sizes is also provided.
U.S. Pat. No. 6,754,894 discloses a wireless information delivery system for delivering software and operating parameter updates to receivers in a broadcast information delivery system. Executable software programs and related operating parameters are changed in a mobile electronic device that is associated with an information delivery system by broadcasting a wireless (e.g., radio) signal containing multiple copies of new data. The mobile device uses the new data to update or to change its software or operating parameters. The number of copies (repetitions) of the new data that are broadcast depends on the expected reception error rate and on the desired probability that the receiver will receive the new data without error. Thus, this method discloses multiple-delivery of the new data to the mobile system for increasing the probability of reception depending on the expected errors.
The prior art discussed above does not overcome all the problems encountered in the field. One of the major problems encountered is the lack of options for selection of commands, which is very pertinent in enhancing the performance of a memory.
There is therefore a need for systems and methods for self-updating memory controllers, such as a NAND controller, a NOR controller, a Micro Controller Unit (MCU), a Micro Processor Unit (MPU), that result in an enhanced memory performance.